The present invention relates in general to substrate manufacturing technologies and in particular to methods and apparatus for the optimization of etch resistance in a plasma processing system.
In the processing of a substrate, e.g., a semiconductor substrate or a glass panel such as one used in flat panel display manufacturing, plasma is often employed. As part of the processing of a substrate for example, the substrate is divided into a plurality of dies, or rectangular areas, each of which will become an integrated circuit. The substrate is then processed in a series of steps in which materials are selectively removed (etching) and deposited. Subsequently, control of the transistor gate critical dimension (CD) on the order of a few nanometers is a top priority, as each nanometer deviation from the target gate length may translate directly into the operational speed of these devices.
In an exemplary plasma process in which a set of gates is created on the substrate, a p-type epitaxial layer is generally disposed on the silicon substrate through chemical vapor deposition. A nitride layer may then be deposited over the epi-layer, then masked and etched according to specific patterns, leaving behind exposed areas on the epi-layer (i.e., areas no longer covered by the nitride layer.) These exposed areas may then be masked again in specific patterns before being subjected to diffusion or ion implantation to receive dopants such as phosphorus, forming n-wells.
Areas of the hardened emulsion are then selectively removed, causing components of the underlying layer to become exposed. The substrate is then placed in a plasma processing chamber on a substrate support structure comprising a mono-polar or bi-polar electrode, called a chuck or pedestal. Appropriate etchant source are then flowed into the chamber and struck to form a plasma to etch exposed areas of the substrate.
Silicon dioxide may then be grown thermally to form field oxides that isolate the n-wells from other parts of the circuit. This may be followed by another masking/oxidation cycle to grow gate oxide layers over the n-wells intended for p-channel MOS transistors later on. This gate oxide layer will serve as isolation between the channel and the gate of each of these transistors. Another mask and diffusion/implant cycle may then follow to adjust threshold voltages on other parts of the epi, intended for n-channel transistors later on.
Deposition of a polysilicon layer over the wafer may then be done, to be followed by a masking/etching cycle to remove unwanted polysilicon areas, defining the polysilicon gates over the gate oxide of the p-channel transistors. At the same time, openings for the source and drain drive-ins are made on the n-wells by etching away oxide at the right locations.
Another round of mask/implant cycle may then follow, this time driving in boron dopants into new openings of the n-wells, forming the p-type sources and drains. This may then be followed by a mask/implant cycle to form the n-type sources and drains of the n-channel transistors in the p-type epi.
However, escalating requirements for high circuit density on substrates may be difficult to satisfy using current plasma processing technologies where sub-micron via contacts and trenches has high aspect ratios. In particular, it is becoming difficult to create relatively deep gate etches, especially when the gate depth is less than the illumination wavelength of the lithographic process. In one commonly used method, a photoresist mask is subsequently trimmed, using chemically dominant etch process. That is, a mask is created in which the CD of features are oversized when compared to the desired result (i.e., pre-etch CD). As the underlying substrate trench is longitudinally etched (i.e., perpendicular to the substrate), the photoresist column is also laterally etched (i.e., parallel to the substrate) or trimmed, to create the final desired gate CD.
Generally, photoresist must be optimized for both the lithographic processes (i.e., contrast, resolution, in-line roughness, etc.) and the integration processes (etch selectivity, chemical stability, ash selectivity, etc.). Those types of photoresist that tend to be susceptible to integration problems, such as chemically dominant etching, are often called “soft.”
Controlling CD with soft photoresist is particularly difficult in sub-100 nm lithographic environments. That is, the photoresist must be both thin enough to avoid collapse of the photoresist column, and thick enough to be consistent with the desired etch selectivity of the etched layer. However, if the photoresist column is disproportionately tall in comparison to its width (i.e., a height to width ratio of greater than 4), the etching process may damage the column, subsequently altering the electrical and functional characteristics of the substrate, and directly impacting substrate performance and manufacturing yield.
For example, as soft photoresist is etched, wiggling or wave-like patterns may be created, potentially causing striations, false micro-loading and random etch-stop. Striations are irregularities in the shape of normal features that create additional exposure areas on the mask. Since the etchant removes unintended substrate material, the resulting electrical and functional characteristics of the wafer can be altered. One effect, for example, may be an increase in the roughness of a column face. Likewise, if a set of photoresist wiggles substantially converge, the resulting mask pattern can partially or completely block the removal of intended substrate material.
False micro-loading occurs when artifacts of the substrate remain on the column trench floor, creating a physically uneven bottom surface. Random edge-stop occurs when column entrances are effectively blocked from the etchant gas during the etching process. In some circumstances, where the column is disproportionately tall and thin (i.e., a height to width ratio of greater than 4), an entire slice of the photoresist column may be accidentally removed or stripped. Additionally, the photoresist column may buckle, bend, or twist by non-uniform stress caused when the lateral etch rate is different than the longitudinal etch rate.
Referring now to FIG. 1, a simplified diagram of plasma processing system components is shown. Generally, an appropriate set of gases is flowed into chamber 102 through an inlet 108 from gas distribution system 122. These plasma processing gases may be subsequently ionized to form a plasma 110, in order to process (e.g., etch or deposition) exposed areas of substrate 114, such as a semiconductor substrate or a glass pane, positioned with edge ring 115 on an electrostatic chuck 116. In addition, liner 117 provides a thermal barrier between the plasma and the plasma processing chamber, as well as helping to optimize plasma 110 on substrate 114.
Gas distribution system 122 is commonly comprised of compressed gas cylinders 124a-f containing plasma processing gases (e.g., C4F8, C4F6, CHF3, CH2F3, CF4, HBr, CH3F, C2F4, N2, O2, Ar, Xe, He, H2, NH3, SF6, BCl3, Cl2, WF6, etc.). Gas cylinders 124a-f may be further protected by an enclosure 128 that provides local exhaust ventilation. Mass flow controllers 126a-f are commonly a self-contained devices (consisting of a transducer, control valve, and control and signal-processing electronics) commonly used in the semiconductor industry to measure and regulate the mass flow of gas to the plasma processing system. Injector 109 introduces plasma processing gases 124 as an aerosol into chamber 102.
Induction coil 131 is separated from the plasma by a dielectric window 104, and generally induces a time-varying electric current in the plasma processing gases to create plasma 110. The window both protects induction coil from plasma 110, and allows the generated RF field to penetrate into the plasma processing chamber. Further coupled to induction coil 131 at leads 130a-b is matching network 132 that may be further coupled to RF generator 138. Matching network 132 attempts to match the impedance of RF generator 138, which typically operates at 13.56 MHz and 50 ohms, to that of the plasma 110.
Generally, some type of cooling system is coupled to the chuck in order to achieve thermal equilibrium once the plasma is ignited. The cooling system itself is usually comprised of a chiller that pumps a coolant through cavities in within the chuck, and helium gas pumped between the chuck and the substrate. In addition to removing the generated heat, the helium gas also allows the cooling system to rapidly control heat dissipation. That is, increasing helium pressure subsequently also increases the heat transfer rate. Most plasma processing systems are also controlled by sophisticated computers comprising operating software programs. In a typical operating environment, manufacturing process parameters (e.g., voltage, gas flow mix, gas flow rate, pressure, etc.) are generally configured for a particular plasma processing system and a specific recipe.
Referring now to FIGS. 2A-B, an idealized cross-sectional view of the layer stack is shown, in which a set of gates are manufactured in a plasma process. FIG. 2A illustrates an idealized cross-sectional view of the layer stack, representing the layers of an exemplar semiconductor IC, prior to a lithographic step. In the discussions that follow, terms such as “above” and “below,” which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of the layer stack, there is shown a layer 204, comprising a semi-conductor, such as polysilicon. Above layer 204 is disposed a photoresist mask layer 208 and a BARC layer 206 is that have been processed through lithography. In this example, a photoresist mask pattern 216 is first lithographically created, and then chemically trimmed in order to create a set of gate trenches 202a-b. 
FIG. 2B shows the cross-sectional view of the layer stack of FIG. 2A after layer 204 has been etched in a plasma processing system in order to create a set of gates by further extending trench 202a-b. In addition, the photoresist mask layer, as well and the underlying semi-conductor layer 204, are laterally trimmed by an etchant by an amount 210.
Referring now to FIGS. 3A-C, an idealized cross-sectional view of the layer stack in which a disproportionately tall soft photoresist column has collapsed during the plasma process. During the etching process, photoresist material may be generally removed either laterally (i.e., parallel to the substrate), or longitudinally (i.e. perpendicular to the substrate.) However, if the column width is sufficiently minimized, the combination of lateral and longitudinal etching produces an effective diagonal etch vector that may remove a substantially large portion of the column, subsequently damaging the underlying substrate.
FIG. 3A illustrates an idealized cross-sectional view of the layer stack, representing the layers of an exemplar semiconductor IC, prior to a lithographic step. At the bottom of the layer stack, there is shown a layer 304, comprising a semi-conductor, such as polysilicon. Above layer 304 is disposed a photoresist mask layer 308 and a BARC layer 306 is that have been processed through lithography. In this example, a photoresist mask pattern is created with a set of trenches 302a-c to create a set of gates.
FIG. 3B shows the cross-sectional view of the layer stack of FIG. 3A after photoresist layer 308 has been etched in a plasma processing system. However, unlike column 216 of FIGS. 2A-B, the relatively thinner columns 316 have been substantially damaged 312 by the etching process. That is, instead of just being reduced in width, the columns are also catastrophically reduced in height.
FIG. 3C shows the cross-sectional view of the layer stack of FIG. 3B after layer 304 has been etched in a plasma processing system, creating a cavity 320 in substrate 304.
Referring now to FIGS. 4A-C, an idealized cross-sectional view of the layer stack in which a disproportionately tall soft photoresist column has twisted during the plasma process. As previously described, photoresist material may be generally removed either laterally (i.e., parallel to the substrate), or longitudinally (i.e. perpendicular to the substrate.) However, if the column width is sufficiently minimized, the combination of lateral and longitudinal etching may create stress on the column sufficient to twist or bend it.
FIG. 4A illustrates an idealized cross-sectional view of the layer stack, representing the layers of an exemplar semiconductor IC, prior to a lithographic step. At the bottom of the layer stack, there is shown a layer 404, comprising a semi-conductor, such as polysilicon. Above layer 404 is disposed a photoresist mask layer 408 and a BARC layer 406 is that have been processed through lithography. In this example, a photoresist mask pattern is created with a set of trenches 402a-c to create a set of gates.
FIG. 4B shows the cross-sectional view of the layer stack of FIG. 4A after photoresist layer 408 has been etched in a plasma processing system. However, unlike column 216 of FIGS. 2A-B, the relatively thinner columns 416 have been substantially twisted 412 by the etching process, subsequently creating non-linear profiles in the underlying substrate 404.
In view of the foregoing, there are desired improved methods for methods and apparatus for the optimization of etch resistance in a plasma processing system.